Aspects of semiconductor manufacturing have focused upon high-speed circuits to obtain a capacitor having a high capacitance. High-capacitance capacitors having a polysilicon/insulator/polysilicon (PIP) structure may be disadvantageous in that capacitance may be reduced as a result of the formation of a natural oxide film due to oxidation occurring at an interface between an upper electrode and a dielectric film and an interface between a lower electrode and the dielectric film. Such oxidation may occur due to the upper and lower electrodes being composed of polysilicon.
In order to eliminate this drawback, a capacitor having an MIM structure has been proposed for applications in semiconductor devices requiring a high Q value. The MIM structure may exhibit a low specific resistance and a low parasitic capacitance caused by an internal depletion. The MIM type capacitor may be connected to a metal line arranged around the MIM type capacitor, or may be connected to source/drain regions of a transistor via contact plugs. Where a highly-integrated semiconductor device using such an MIM type capacitor is manufactured, a damascene process may be used to form a plurality of electrodes and a plurality of lines for the capacitor, in place of an etching process. The damascene process may involve patterning an interlayer insulating film to form capacitor electrodes or lines regions, namely, trenches; gap-filling a metal material in the trenches, and planarizing the metal material using a chemical mechanical polishing (CMP) method. The MIM capacitor may be formed between a first metal line composed of copper and a second metal line in order to eliminate the interlayer insulating film planarizing process.
However, such a method of forming a capacitor may be disadvantageous since it may be necessary to use a mask for the formation of the MIM capacitor, and an additional mask for the formation of the line structure, which in turn, increases overall manufacturing costs.